Get A Designer’s Guide to Built-In Self-Test PDF

By Charles E. Stroud

ISBN-10: 0306475049

ISBN-13: 9780306475047

ISBN-10: 1402070500

ISBN-13: 9781402070501

A fresh technological develop is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept used to be first proposed round 1980 and has grown to turn into essentially the most vital trying out strategies on the present time, in addition to for the longer term. This ebook is written from a designer's point of view and describes the foremost BIST methods which were proposed and applied due to the fact 1980, besides their benefits and barriers. The BIST techniques comprise the integrated good judgment Block Observer, pseudo-exhaustive BIST concepts, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection concepts for online checking out. specific consciousness is paid to system-level use of BIST to be able to maximize the advantages of BIST via diminished checking out time and price in addition to excessive diagnostic solution. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied varieties for normal constructions and common sequential common sense, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his examine and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs besides persisted paintings within the zone of BIST for normal sequential good judgment and mixed-signal structures. He holds 10 US patents (with five extra pending) for varied kinds of BIST methods. consequently, the writer brings a special mix of data and adventure to this functional consultant for designers, try engineers, product engineers, procedure diagnosticians, and managers.

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9943% [277]. Therefore, there was no need to continue with test development for higher fault coverage since the faults that were not detected were those faults that were the least likely to occur. 5% unweighted bridging fault coverage. 9% indicating that the bridging faults being detected by this set of tests were those that were the least likely to occur. This case contradicts the notion that high stuck-at gate-level fault coverage implies high bridging fault coverage. 8 Statistical Fault Sampling Another important method for reducing the total number of faults to be simulated and the resulting fault simulation time is to simulate a subset of the complete set of faults.

This is typically referred to as at-speed testing and is important since it facilitates the detection of faults that lead to excessive delay (referred to as delay faults) in an otherwise working CUT. During manufacturing testing, the clock frequency can be varied to determine the maximum speed at which the CUT will perform correctly, such that the BIST can be used at manufacturing testing for speed sorting the devices or to determine the timing margins of the fabricated devices under various voltage and temperature conditions.

A “good” circuit is assumed to be defect-free, but this assumption is only as good as the quality of the tests being applied to the manufactured design. Once again, fault simulation provides a quantitative measure of the quality of the set of tests. 1 with one exception. In addition to the input test vectors, a list of faults that are to be emulated in the CUT is also applied to the fault simulation environment [4], The fault simulator emulates each fault (or set of faults) in the list and applies the test vectors.

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A Designer’s Guide to Built-In Self-Test by Charles E. Stroud

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